SLX understands the exact behavior of an application by utilizing both static as well as dynamic compiler technology to identify all data- and control-dependencies and build up a complete application model. This includes the call graph of an application, read and write accesses to local, heap and global variables and a complete understanding of memory accesses. For parallel applications, existing communication and synchronization patterns are also analyzed.
A pattern-based framework identifies missed opportunities for additional parallelism with different levels supported such as: task-, pipeline-, data- level parallelism, runnable-level parallelism for AUTOSAR applications or the automatic extraction of pipeline level parallelism targeting FPGA-based platforms. The framework is easily adaptable to the requirements of additional industry requirements
Timing information, either automatically derived from SLX’s platform model or from target traces, supplements the application model with the necessary timing information of the target behavior. This considers different types of processor cores, memory hierarchies of the target platform and the interconnect architectures. A built-in reconfigurable cache analyzer is included on top of Silexica’s platform modeling infrastructure allowing users to specify a diverse set of memory hierarchies and configuration parameters.
Numerous input formats are supported including applications written in sequential C/C++, using POSIX threads, dataflow, process networks and task graph specifications and AUTOSAR compliant source code. For an example of the opportunities with SLX in AUTOSAR projects, watch this short demonstration video.
Static and Dynamic
Source Code Analysis
Cache, Memory and Communication Analysis
C/C++, data-flow, task-graphs, OSEK tasks, POSIX Threads
Sophisticated optimization techniques allow for the optimal mapping of processes to heterogeneous cores and accelerators, the fastest mapping of logical channels to platform interconnects and memories, and the most effective memory allocation for the buffers used for inter-process communication. Available optimization criteria are performance, power and memory.
SLX tools provide advanced simulation of the target behavior of the application and provides detailed feedback on the execution behavior, task states and platform utilization of processors and communication architecture. (Read more about communication contention in this technical blog post). Memory and contention modeling techniques assure the right trade-offs between accuracy and speed while simulating the target platform behavior. Optionally, measured or estimated power consumption information can be used for a power-optimized distribution with an analysis on required power states and detailed power and energy consumption of the application.
The user-editable, abstract multicore platform model distributes an application to a fixed or multiple platforms at the same time. It enables architects to search for the ideal off-the-shelf multicore platform for a given application and supports “what if” analysis with respect to software and hardware changes to drive exploration, design, and evolution for next-generation multicore systems.
SLX can predict the effects of changes in the application workload or analyzes the potential application speed-up of adding processors, memories, and hardware accelerators into the current multicore architecture. It creates a faster turn-around time compared to state-of-the-art instruction-set simulators by an order of magnitude to significantly improve the design of next generation products.
Power-, performance-, and memory-driven SW distribution
Optimized task schedules under tight timing constraints
Selection of DVFS power states to decrease peak and average power
Architecture Exploration and Multicore Communication Analysis
SLX directly ties back any findings made during the Analyze and Optimize phases to the original source code lines and its variables. This allows unique capabilities in giving accurate and comprehensive user feedback and in automatic source-to-source rewriting.
To help users migrate their existing sequential code, either powerful hints are shown to the user to rewrite their source code or existing code can be rewritten automatically by inserting pragmas for existing shared memory APIs or customized internal workflows.
For existing parallel code, e.g. process network or AUTOSAR specifications, a powerful source-to-source framework inserts APIs for task management, synchronization, and communication, selected from the runtime environments and operating systems available for the target multicore platform. The output can be compiled directly using the platform’s native compiler toolchains and can be deployed to the target.
Clear suggestions to spend less time during multicore migration
Mapping dependent code generation for multicores
Automatic insertion of pragmas (OpenMP, HLS, etc..)
ABSOLUTE CODE UNDERSTANDING
Our technology analyzes your software to fully understand your code and its interdependencies based on static, dynamic and semantic code analysis.
FASTER TIME TO MARKET
Automatic analysis, partitioning and distribution across cores saves time and resources, improving the productivity of your team and making your software design flow more flexible to hardware changes.
MEET CHALLENGING REQUIREMENTS
Advanced simulation techniques forecast the target behavior of the application driven by various optimization criteria and environment constraints.
For System Architects working with software models, or Developers working with in-house, open source, commercial source and binary code, the traditional methods of software optimization are not scalable for multicore systems anymore.
To fully understand the application behavior on a multicore system, a full and precise analysis of software interdependencies is required. In order to understand system behavior and explore opportunities for performance gains and power saving, a tool is needed to provide deep insights into the software interdependencies that occur during execution.
SLX is a multicore development tool that provides software execution insights into hardware and software interdependencies. It allows for code architecting and refactoring to achieve the most efficient utilization of CPU, DSP, FPGA and other acceleration engines on multicore systems.
Optimizing C/C++ applications on complex multicore SoCs requires a complete understanding of the software architecture and its behaviour on the hardware. Developers are challenged with the task of optimizing sequential and parallel code for multicore SoCs that comprise a variety of compute engines. For the most efficient utilization of CPUs, DSPs and FPGAs, a full understanding of the code structure and interdependencies between applications, threads and variables is required for streamlined software development, guided refactoring and software design optimization.
SLX C/C++ enables the development and optimization of concurrent C/C++ applications for heterogeneous multicore platforms with unparalleled actionable insights. This allows for software professionals to achieve an optimized software architecture and optimal performance for a specific code on a particular multicore SoC. SLX blends hardware understanding with code analysis to give unrivalled insights into the application’s execution while providing a feedback loop to the original source code to provide full traceability.
SLX analyzes C/C++ code and provides a deep understanding of the execution flow, application hot spots and software interdependencies, to enable code optimization for heterogeneous multicore SoCs with FPGAs. Acceleration opportunities are available in FPGA enabled SoCs through partitioning C/C++ code between hardware and software compute elements. Given the number of options multicore SoCs provide, design decisions need to be based on a systematic exploration process. However, this is complex as there is a variety of options in how software functionality can be implemented in hardware.
SLX provides a system view of the application to identify hot spots that offer the greatest potential for increased system performance through FPGA offload. With SLX, users are provided with deep insights into C/C++ software interdependencies needed for code refactoring to implement the changes for FPGA off-loading. SLX optimizes software performance on CPU cores and identifies code to be partitioned. SLX analyzes source code to simplify the task of understanding the opportunities for software and hardware acceleration. Read more in this news story here or watch the FPGA demo video by clicking the button.
SLX Scheduling Design provides solutions for task-based systems with C/C++, AUTOSAR Classic or AMALTHEA inputs. By giving a full understanding of the dependencies between functions and tasks, efficient multicore schedules can be generated.
By using the power of SLX’s Function Level Parallelism and Task Level Parallelism capabilities, power consumption can be reduced while still meeting crucial system latency constraints. SLX for Scheduling Design operates in three phases, Analyze, Optimize and Integrate.
Customer Success Stories
Here is what clients have to say about us
“In the near future, deep challenges lie in optimizing communication and automotive applications onto multicores.
We have successfully integrated the SLX Tool Suite into our multicore development flow to address these challenges.”
“We have been working with Silexica on power modelling analysis for some time now and are consistently happy with the quality of the estimates produced by SLX and the professionalism of the team that is working with us.
We hope to continue this partnership and make a significant impact on our SoC exploration phase with SLX.”
“Preparing C/C++ code for FPGAs is often very time consuming as you prepare for the migration.
By using SLX in the future we plan to analyze our applications to make the next steps of performance estimation and hardware/software partitioning quicker with better performance through more pragmas.”