SLX-FPGA-slx-fpga

SLX FPGA

Accelerate the Journey
from C/C++ to FPGA

Product Brief

SLX FPGA helps to convert your C/C++ code into an FPGA more easily, faster, and with higher performance. Leveraging standard HLS (High Level Synthesis) tools from FPGA vendors, SLX FPGA tackles the challenges associated with the HLS design flow including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, where to insert pragmas, and how to determine optimal SW/HW partitioning. Using SLX FPGA enables you to get to market faster by leveraging the benefits of HLS for FPGA design entry. These benefits include improved productivity through designing at a higher level of abstraction, orders of magnitude faster simulation than traditional RTL simulation, and higher QoR through high-level optimizations and design space exploration.

  • Enable Synthesizability
  • Maximize Performance
  • Develop Faster
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Watch the video: SLX FPGA: Accelerate the Journey from C/C++ to FPGA

Features and Capabilities

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C/C++ coding guidelines for HLS compilers are extensive and can be over 1000+ pages of documentation that needs to be comprehended when writing or refactoring C code for HLS synthesis. SLX FPGA eliminates the need to be an expert in coding for HLS by:

  • Identifying C/C++ code which is non-synthesizable
  • Performing automatic code refactoring for many common C libraries
  • Providing guided code refactoring by supplying code examples to help re-write the code to make it synthesizable
1. CONVERT NON-SYNTHESIZABLE C:C++ CODE-slx-fpga

C/C++ code is typically executed sequentially on standard processors but implementing functions in dedicated hardware allows operations to be executed in parallel, accelerating the execution of the code in hardware. SLX FPGA analyzes and detects C/C++ code that can be accelerated in hardware by executing in parallel.

2. PARALLELISM DETECTION-slx-fpga

After identifying functions that can be implemented to execute in parallel, SLX FPGA performs analysis of the functions to determine the theoretical maximum for the achievable speedup. Using Silexica’s proprietary algorithms, SLX FPGA then determines the ideal implementation of the parallel function based on user supplied constraints, ensuring an optimized implementation.

3. HW Optimization

Once the optimized hardware implementation is determined, SLX FPGA inserts HLS Pragmas to direct the HLS compiler on how to implement the function in hardware.

4. Pragma Insertion

Videos Show all Videos

SLX FPGA Demo at XDF 2019 - Optimizing Financial Algorithms for HLS with SLX FPGA
Oct 17, 2019 5min
SLX FPGA Demo at XDF Europe 2019 - Optimization of Aerospace/Defense Algorithm for HLS with SLX FPGA
Oct 17, 2019 5min

Training

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We offer full day training classes now!
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