Features and Capabilities
C/C++ coding guidelines for HLS compilers are extensive and can be over 1000+ pages of documentation that needs to be comprehended when writing or refactoring C code for HLS synthesis. SLX FPGA eliminates the need to be an expert in coding for HLS by:
- Identifying C/C++ code which is non-synthesizable
- Performing automatic code refactoring for many common C libraries
- Providing guided code refactoring by supplying code examples to help re-write the code to make it synthesizable
C/C++ code is typically executed sequentially on standard processors but implementing functions in dedicated hardware allows operations to be executed in parallel, accelerating the execution of the code in hardware. SLX FPGA analyzes and detects C/C++ code that can be accelerated in hardware by executing in parallel.
After identifying functions that can be implemented to execute in parallel, SLX FPGA performs analysis of the functions to determine the theoretical maximum for the achievable speedup. Using Silexica’s proprietary algorithms, SLX FPGA then determines the ideal implementation of the parallel function based on user supplied constraints, ensuring an optimized implementation.
Once the optimized hardware implementation is determined, SLX FPGA inserts HLS Pragmas to direct the HLS compiler on how to implement the function in hardware.