SLX

The perfect programming solutions for your multicore project

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For System Architects working with software models, or Developers working with in-house, open source, commercial source and binary code, the traditional methods of software optimization are not scalable for multicore systems anymore.

To fully understand the application behavior on a multicore system, a full and precise analysis of software interdependencies is required. In order to understand system behavior and explore opportunities for performance gains and power saving, a tool is needed to provide deep insights into the software interdependencies that occur during execution.

SLX is a multicore development tool that provides software execution insights into hardware and software interdependencies. It allows for code architecting and refactoring to achieve the most efficient utilization of CPU, DSP, FPGA and other acceleration engines on multicore systems.

SLX

FPGA

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SLX combines a deep understanding of legacy source code, how it is executed and the implications of a system that enables the partitioning of applications into software to run on several processors, and hardware to be mapped to an FPGA. It gives comprehensive processor modeling, and characterization of the timing and resource capabilities of the FPGA. SLX searches for parallelism patterns from static and dynamic information.

The design space is explored to fully optimize hardware/software partitioning. Pragmas are automatically inserted based on the optimization decisions for the parallelization of the software and for guiding the High Level Synthesis (HLS) process for the hardware implementation. SLX uniquely connects its analysis and advice to your source code, simplifying your task of understanding the opportunities for, or blockers of, parallelism and hardware acceleration.

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Static and Dynamic Source Code Analysis

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Automatic SW/HW Partitioning

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Automatic insertion of pragmas (OpenMP, HLS)

ANALYZE

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Analyze code

SLX builds a complete application model from sophisticated compiler technology utilizing both static as well as dynamic analysis to identify and reason about all data and control dependencies. The model includes the application call graph, read and write accesses to local, heap and global variables, and a complete understanding of memory accesses within the system architecture.

A pattern-based framework identifies potential opportunities to transform your application to expose more parallelism. SLX identifies:

  • Data-Level, Task Level and Pipeline-Level parallelism
  • Offloading opportunities for custom cores and hardware accelerators
  • Parallelism potential blocked by dependencies or irregular control patterns

Based on the timing and resource information from SLX’s platform models, the designer’s analysis is focused only on the parts of the application that can provide an effective gain. This eases the designer task, and increases productivity.

OPTIMIZE

Find the Optimal Hardware/Software partitioning

Based on the platform models, SLX is able to determine the timing and resource consumption for the implementation of a detected parallelism pattern, running in a processor as software, or in the FPGA as a hardware accelerator. An optimization algorithm utilizes this information to calculate the final partitioning of the application, and is able to:

  • Provide graphical representation of the partitioning, directly HW linked with the source code
  • Report global and local performance improvement for each detected parallelism pattern
  • Report the final resource consumption on the FPGA, for the calculated hardware/software partitioning
  • Provide recommendations on the most beneficial partitioning for the target FPGA-enabled SoC

SLX allows the user to override the calculated partitioning, and manually test alternative implementations. This workbench approach guarantees to keep the designer in the loop, and exploit human ingenuity while increasing productivity.

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INTEGRATE

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Guide and Rewrite

SLX helps users migrate their existing application by automatically rewriting the code once a partitioning has been established. For the software portions of the application that exhibit parallelism, OpenMP 4.5 Pragmas are inserted to guarantee a multithreaded implementation in the target platform. Xilinx pragmas are inserted for the hardware parts of the application, tuned to guarantee an efficient implementation for the resulting accelerators.

SLX also provides code refactoring hints for the parts of the application that could not be parallelized or implemented in hardware, pin-pointing the reasons that impeded these activities. SLX has an end-to-end integration with Xilinx Vidado HLS and SDSoC tools, that creates a way between legacy code and a partitioned application running on the target FPGA-enable SoC.

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