For System Architects working with software models, or Developers working with in-house, open source, commercial source and binary code, the traditional methods of software optimization are not scalable for multicore systems anymore.
To fully understand the application behavior on a multicore system, a full and precise analysis of software interdependencies is required. In order to understand system behavior and explore opportunities for performance gains and power saving, a tool is needed to provide deep insights into the software interdependencies that occur during execution.
SLX is a multicore development tool that provides software execution insights into hardware and software interdependencies. It allows for code architecting and refactoring to achieve the most efficient utilization of CPU, DSP, FPGA and other acceleration engines on multicore systems.
SLX FPGA helps to convert your C/C++ code into an FPGA bitstream easier, faster, and with higher performance. Leveraging standard HLS (High Level Synthesis) tools from FPGA vendors, SLX FPGA tackles the challenges associated with the HLS design flow including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, where to insert pragmas, and how to determine optimal SW/HW partitioning. Using SLX FPGA enables you to get to market faster by leveraging the benefits of HLS for FPGA design entry. These benefits include improved productivity through designing at a higher level of abstraction, orders of magnitude faster simulation than traditional RTL simulation, and higher QoR through high-level optimizations and design space exploration.
SLX FPGA addresses the challenges of using a HLS design flow by performing static and dynamic code analysis and providing deep insights in to the user’s C/C++ code. Through this code analysis, SLX FPGA identifies non-synthesizable C/C++ code, detects non-hardware aware data types, and pinpoints parallelism within the SW that can be implemented in HW for acceleration. SLX FPGA provides guided and automatic code refactoring for HLS synthesizability helping to solve the biggest barrier and most time-consuming aspects of using HLS design flows. SLX FPGA then uses the detected parallelism to automatically generate and insert HLS pragmas which optimize the design for performance and area utilization.
Clear guidance into HLS Synthesizablity of C/C++ code
HW/SW Partitioning Exploration
Automatic insertion of pragmas (OpenMP, HLS)