The SLX technology understands the exact behavior of an application by analyzing its source code. It uses sophisticated compiler technology by utilizing both static as well as dynamic compiler technology to identify all data- and control-dependencies and build up a complete application model. This includes the call graph of an application, read and write accesses to local, heap and global variables and a complete understanding of memory accesses within the memory hierarchy. For parallel applications, existing communication and synchronization patterns are analyzed as well.
A pattern-passed framework allows to identify missed opportunities for additional parallelism. Different levels of parallelism are supported, such as task-, pipeline-, and data- level parallelism for embedded high performance computing code, runnable-level parallelism for AUTOSAR specific applications or the automatic extraction of pipeline level parallelism targeting FPGA-based platforms. The framework is easily adaptable to the requirements of additional industry requirements
Timing information, either automatically derived from Silexica’s platform model or from target traces, supplements the application model with the necessary timing information of the target behavior. Here, not only different types of processor cores are taken into account, but also the different memory hierarchies of the target platform as well as different interconnect architectures. A built-in reconfigurable cache analyzer is included on top of Silexica’s flexible platform modeling infrastructure. It allows users to specify a diverse set of memory hierarchies and configuration parameters.
A large number of different inputs formats are supported. This includes applications written in sequential C/C++, using POSIX threads, dataflow, process networks and task graph specifications and AUTOSAR compliant source code.
Static and Dynamic
Source Code Analysis
Cache, Memory and Communication Analysis
C/C++, data-flow, task-graphs, OSEK tasks, POSIX Threads
Sophisticated optimization techniques allow to automatically choose the optimal mapping of processes to heterogeneous cores and accelerators, the fastest mapping of logical channels to platform interconnects and memories, and the most effective memory allocation for the buffers used for inter-process communication. Available optimization criteria are performance, power and memory, while a large number of different real-time and resource constraints are respected at the same time.
The tooling does not stop in presenting the distribution decisions to the user. Advanced simulation techniques simulate the target behavior of the application and give detailed feedback on the execution behavior, detailed task states and platform utilization of both processors and communication architecture. Advanced memory and contention modeling techniques assure the right trade-offs between accuracy and speed while simulating the target platform behavior. Optionally, measured or estimated power consumption information can be used for a power-optimized distribution with an analysis on required power states and detailed power and energy consumption of the application.
The user-editable, abstract multicore platform model allows not only to distribute an application to a fixed platform, but to multiple platforms at the same time as well. It enables architects to search for the ideal off-the-shelf multicore platform for a given application and supports “what if” analysis with respect to software and hardware changes to drive exploration, design, and evolution for next generation multicore systems.
It predicts the effects of changes in the application workload or analyses the potential application speed-up of adding processors, memories, and hardware accelerators into the current multicore architecture. It allows a faster turn-around time compared to state-of-the-art instruction-set simulators by an order of magnitude to significantly improve the design of next generation products.
Power-, performance-, and memory-driven SW distribution
Optimized task schedules under tight timing constraints
Selection of DVFS power states to decrease peak and average power
Architecture Exploration and Multicore Communication Analysis
Silexica’s unique source-to-source compiler technology allows a developer to significantly increase the turn-around time for software changes and his productivity level, allowing him to focus on his requirements instead of wasting time in useless iterations.
Silexica’s technology allows to directly tie back any findings made during the Analyze and Optimize phase to the original source code lines and its variables. This allows unique capabilities in given accurate and comprehensive user feedback and in automatic source-to-source rewriting.
To help users migrate their existing sequential code, either powerful hints are shown to the user to rewrite their source code or existing code can be rewritten automatically by inserting pragmas for existing shared memory APIs or customized internal workflows.
For existing parallel code, e.g. dataflow, process network or AUTOSAR specifications, a powerful source-to-source framework insert APIs for task management, synchronization, and communication, selected from the runtime environments and operating systems available for the target multicore platform. The output can be compiled directly using the platform’s native compiler toolchains and can be deployed to the target.