SLX Version 2019.2 Delivers 35X HLS Performance Improvement with SLX FPGA & Adds Multi-process support with SLX C/C++

July 18, 2019 – Silexica has released the SLX development tools version 2019.2 with major improvements to the FPGA and C/C++ products. The SLX FPGA product helps developers prepare and optimize C/C++ code for High Level Synthesis in the Xilinx® Vivado® HLS design flow. Version 2019.2 delivers an average of 35X performance improvement with automatic HLS pragma insertion compared to no HLS pragmas.  The SLX C/C++ product adds support for multi-process analysis, shared libraries, remote file systems, and improvements in graphical visualization and performance estimations.

 

SLX FPGA New Features and Enhancements

  • Guided Code Transformations for Synthesizability: SLX FPGA guides the user with detailed examples on how to refactor non-synthesizable code so that it is supported by the Xilinx HLS compiler. The refactored code is presented side-by-side with the original code.
  • Hardware Aware Parallelism Extraction: This feature extends the existing algorithms to discover fine grained opportunities for Data-Level Parallelism and Pipeline-Level Parallelism. This enables SLX FPGA to insert more detailed HLS pragmas into the application and have more control over the achieved performance/area trade-offs.
  • Code Refactoring Wizard: After the optimal combination between HLS pragmas and their parameters has been extracted, this wizard presents a side-by-side comparison between the original and the generated code and allows the user full control over which pragmas are ultimately inserted in the code. The code refactoring wizard also allows modifications to the generated code before the HLS tools are invoked for synthesis.
  • Zynq® DevKit Support: Additional Xilinx Zynq development kits were added to the set of supported platforms. This also includes support for Avnet®’s Ultra96.
  • Xilinx DSA Importer: It is now possible to import existing Xilinx Design Specification Archives (DSA) into SLX FPGA. This enables development engineers to receive a base system from the platform team and perform hardware optimization and partitioning based on the available resources on the FPGA chip.

SLX C/C++ New Features and Enhancements:

  • Multi-Process Analysis: SLX C/C++ has strengthened the multi-process analysis. Multiple processes communicating by using shared memory can be investigated in the Code Analysis Graph and Memory Analysis Table. The protection analysis has been extended to support the use of (named) POSIX semaphores, which are often used to protect shared memories across multiple processes.
  • Visualization: The graphical visualization in the Code Analysis Graph has been extended with a layer for processes. The new layer allows the investigation of the inter-process relationships. In addition, the property sections show detailed information about processes, threads, functions, and variables. Furthermore, all tables in the GUI provide advanced filter and export facilities.
  • User-Defined Thread Names: SLX C/C++ has added support for user-defined thread names. Using the function pthread_setname_np users can name the threads of the application. The given name will be used by SLX C/C++ in the analysis results.
  • Function Costs: SLX C/C++ performance estimation gives separate estimates for each processor type defined in the platform to support the user with mapping and deployment decisions.
  • Remote File Systems: SLX C/C++ supports trace and analysis on one file system, whereas the results can be investigated in the GUI running on a different (file) system (e.g., this enables the usage of SLX C/C++ within a Docker container while running the GUI on the host).
  • Shared libraries: SLX C/C++ allows instrumenting and tracing of applications which use POSIX shared libraries. SLX C/C++ supports POSIX load-time (dynamic) linking of multiple instrumented binaries. Run-time linking, with dlopen, and Windows dynamic linking is not supported.

 

SLX 2019.2 represents a significant step forward in the capabilities and feature improvements in the tool, extending Silexica’s position as a leader in C/C++ multi-core and FPGA programming analysis. Also, please contact us if you are interested in seeing a live demo or exploring an evaluation of SLX FPGA!