Silexica’s New SLX FPGA 2020.4 Ushers in a New Level of Usability
San Jose, CA – January 11, 2021 – Silexica (silexica.com) has announced the release of SLX FPGA 2020.4 to expand the adoption of high-level synthesis (HLS) for FPGA designs. This release includes a new interactive, task-based flow that walks HLS users through the design flow from start to finish. The task-based flow recommends next steps and possible analysis results relevant to the user at each step in the flow. In addition, SLX FPGA 2020.4 incorporates optimizations to the profiling capability that allow designers to understand the execution costs from an FPGA implementation vs a CPU implementation and quickly identify bottlenecks, improving time-to-market.
“The release of SLX FPGA 2020.4 represents another significant step forward in bridging the gap between software development and designing an FPGA,” said Jordon Inkeles, VP of Product at Silexica. “SLX FPGA 2020.4 includes major improvements towards usability to help users achieve better results in less time. By providing deeper insights into the HLS flow and guidance to the user, the new release lowers the barriers of HLS adoption.”
SLX FPGA 2020.4 also includes support for the new SLX Plugin, the first commercially available plugin to expand the capabilities of Xilinx’s Vitis Unified Software Platform. The SLX Plugin is designed to further expand the reach of FPGAs for software developers, enabling the addition of new pragmas and compiler optimizations when designing for FPGAs using HLS. When combining SLX FPGA with automatic pragma insertion and the new SLX Plugin providing new pragmas, new levels of performance and area optimization can be achieved in hardware from C/C++ specifications.
New features and enhancements to SLX FPGA 2020.4 include:
- A new interactive, task-based flow which provides a significantly improved user flow to expand the adoption of the HLS-based FPGA design.
- Improvements in the profiling capability to help designers quickly identify and remove bottlenecks.
- Support for the SLX Plugin enabling the automatic insertion of new pragmas and compiler optimizations automatically.
- Multi-dimensional array support for better performance.
- Support for Xilinx’s Vitis HLS compiler and a new Vitis HLS Importer to make getting started easier for new projects.
- Support from Xilinx’s Versal Adaptive Compute Acceleration Platform.
Overcome HLS Challenges with SLX FPGA
Adopting an HLS methodology presents challenges that must be considered and overcome during the design process. SLX FPGA tackles the challenges associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detection of application parallelism, and pragma insertion location to help engineers prepare and optimize their C/C++ application code for HLS.
Please contact us if you are interested in seeing a live demo or exploring an evaluation of SLX FPGA.
Silexica provides software development tools allowing technology companies to take innovative IP and intelligent products from concept to deployment. Enabled by metrics-driven software analysis and execution behavior insights, the SLX programming tools accelerate the journey from software to application-specific hardware.
Founded in 2014, Silexica is headquartered in Germany with offices in the US and Japan. It serves innovative companies in the automotive, robotics, wireless communications, aerospace, and financial industries and has received $28M in funding from international investors.
This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No 858051.