Silexica Launches First Commercially Available High-Level Synthesis (HLS) Plugin
The SLX Plugin extends Vitis HLS capabilities as part of Xilinx’s open source initiative
San Jose, CA – December 9, 2020 – Silexica (silexica.com) has announced the first commercially available plugin to support Xilinx’s Vitis Unified Software Platform. Designed to expand the capabilities of the Vitis HLS tool, the SLX Plugin enables the addition of new pragmas and compiler optimizations when designing for FPGAs using high-level synthesis (HLS). The SLX Plugin contains the new Loop Interchange pragma, the first of many planned pragmas from Silexica that provide automatic loop transformations. In addition, the SLX Plugin contains several automatic compiler transformations that complement Vitis HLS transformations for improved performance.
The SLX Plugin is designed to further expand the reach of FPGAs for software developers. When combining SLX FPGA, with automatic pragma insertion and the new SLX Plugin providing new pragmas, new levels of performance and area optimization can be achieved in hardware from C/C++ specifications. The SLX Plugin further accelerates the path from C/C++ to FPGA.
“The collaborative efforts between Xilinx and Silexica to extend Vitis HLS with a loop transformation add-on is in line with Xilinx’s Open Source strategy and has been a win for all parties,” said Ramine Roane, Vice President of Marketing at Xilinx. “With Silexica’s new plugin, our customers can now get access to application-specific HLS compiler transformations that help to further optimize their designs”
Key SLX Plugin features include:
- Loop Interchange pragma enables reordering of nested loops to remove dependencies that prevent improved parallelism, pipelining, and memory access regularity
- IR Design Optimizations improve an HLS design’s internal program representation before the RTL code is generated, helping to boost Vitis HLS’ capabilities for automatic relocation of loop invariant memory accesses.
- Transformation checks are enabled for new pragmas and IR design optimizations preventing compiler transformation from being applied when not safe or legal.
“The SLX Plugin demonstrates the value partners can bring during open source initiatives,” said Jordon Inkeles, Vice President of Product at Silexica. “Our first pragma is just the beginning, we are planning many more loop interchange pragmas in the next 12-months to further enable software engineers using FPGAs.”
To get early access to the SLX Plugin for Vitis 2020.2, sign up on our website or contact us. The SLX Plugin is an add-on to the Vitis HLS compiler and can operate stand-alone. SLX FPGA 2020.4 supports automatic optimization and insertions of new pragmas provided with the SLX Plugin.
Maximizing Design Performance
Adopting an HLS methodology presents challenges that must be considered and overcome during the design process. SLX FPGA tackles the challenges associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, and pragma insertion location to help engineers prepare and optimize their C/C++ application code for HLS.
Silexica provides software development tools reducing time-to-market of innovative software IP and intelligent products. Enabled by deep software analysis, heterogeneous hardware awareness and quick design space exploration, the SLX programming tools accelerate the journey from software to application-specific hardware systems, democratizing accelerated computing.
Founded in 2014, Silexica is headquartered in Germany with offices in the US and Japan. It serves innovative companies in the automotive, robotics, wireless communications, aerospace, and financial industries and has received $28M in funding from international investors.
This project has received funding from the European Union’s Horizon 2020 research and innovation program under grant agreement No 858051.