OUR DOCUMENTATION
READING WHAT’S BEHIND
Product Briefs
User Guides
App Notes
All
SLX FPGA
Optimizing acceleration kernels using SLX FPGA and the bottom-up flow
SLX FPGA
In this application note, Silexica uses the Vitis quantitative finance library implementation of the Vasicek Model (v_model) as a reference design to show how designers can use SLX FPGA to optimize a kernel when using Vitis bottom-up flow.
Customer Success Stories
White Papers and Tech Articles
All
SLX FPGA
SLX C/C++
High-Level Synthesis: Can it outperform hand-coded HDL?
SLX FPGA
Our latest white paper highlights how SLX FPGA, on a real-world case study, can both automatically insert pragmas for better performance and provide deep code insights to guide code refactoring. The final #HLS implementation optimized with SLX FPGA is 64% faster compared to the handwritten HDL implementation and is completed in a fraction of the time!
Adaptive Beamformer: An HLS Optimization Case Study with SLX FPGA
SLX FPGA
In this paper, the latency and utilization metrics of an adaptive beamforming algorithm optimized by SLX FPGA are compared to the metrics of the same algorithm hand-optimized by an HLS expert. SLX FPGA achieves a lower latency and cuts development time from weeks down to minutes, using an automated flow that eliminates the need for knowledge of the algorithm and target architecture.on embedded devices can be addressed.
Accelerating Financial Applications With SLX FPGA
SLX FPGA
In this paper, two implementations of computation intensive models for pricing options are discussed, namely the Black-Scholes and Heston pricing models. This white paper demonstrates how engineers creating FPGA-based hardware accelerators for financial market models can take advantage of SLX FPGA.
Using SLX FPGA for performance optimization of SHA-3 for HLS
SLX FPGA
Can an HLS optimization tool outperform expert-level hand-optimizations? This white paper examines how SLX FPGA is used to optimize a secure hash algorithm.
Facilitating High Level Synthesis from MATLAB generated C/C++
SLX FPGA
A use case for HLS is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler.
Optimizing Deep-Learning Inference for Embedded Devices
SLX C/C++
This white paper highlights how different challenges related to the deployment (inference) of artificial neural networks (ANNs) on embedded devices can be addressed.
SLX Multi-Objective Optimization (MOPT)
SLX C/C++
Simultaneous optimization to improve power and performance with SLX
Pushing Performance: Analysis and Optimization of Multicore Communication with SLX
SLX C/C++
How SLX can predict performances, manage communication contention and automatically map tasks to get the best out of your multicore platform.
Improving Execution Predictability on Linux with SLX
SLX C/C++
Assessing the impact of deterministic programming models on predictability of test results
Multicore Software Design for an LTE Base Station
SLX C/C++
Using SLX for Multicore Software Design of an LTE Base Station
Article - Silexica’s Hardware/Software Co-design
SLX C/C++
The Linley Group's Microprocessor Report takes an in-depth look into the features of SLX
Article - Silexica: Mastering Multicore
SLX C/C++
Paul McLellan meets our US team and takes an in-depth look at SLX where he compares manual with automated code analysis
