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SLX FPGA

Accelerate the Journey from C/C++ to FPGA

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SLX FPGA

Optimizing an OpenCL AI Kernel for the data center using SLX FPGA and Vitis HLS 20.2

SLX FPGA

This application note is written for FPGA application developers using Vitis HLS 20.2 version. Read how SLX FPGA accelerates an AI-related face detection design example, leveraging the bottom-up flow of Xilinx's Vitis 2020.2 and Alveo U280 accelerator card.

Using the SLX Plugin for Vitis HLS to optimize MRI Reconstruction

SLX FPGA

In this application note, the SLX Plugin for Xilinx´s Vitis HLS allows developers to take control of the iteration order in loop nests with a simple pragma using an MRI reconstruction example.

Optimizing an OpenCL Kernel for the data center using SLX FPGA and Vivado HLS 20.1 or earlier

SLX FPGA

This application note is written for FPGA application developers using Vivado HLS versions 20.1 and earlier. Read how SLX FPGA accelerates a Fintech design example, leveraging Xilinx's Vitis Platform's bottom-up flow, Alveo U200 accelerator card, and the Vitis quantitative finance library.

customer success story – RICOH-documentation

Using SLX FPGA and HLS to optimize a complex image processing algorithm

Denso – customer success story-documentations-test-2020

Migrating existing automotive control software to multicore ECUs

Huawei – customer success stories-documentations-test-2020

Using Silexica’s tools to accurately estimate power efficiency gains of new technologies

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SLX FPGA

SLX C/C++

Using SLX FPGA for Performance Optimization and Design Space Exploration of a C++ Based Post-Quantum Cryptographic Algorithm

SLX FPGA

In close collaboration with NYU Tandon School of Engineering, Silexica presents a new paper to describe its use of the SLX FPGA tool to implement the signature verification portion of the Rainbow post-quantum cryptography algorithm in an FPGA. The tool's automated optimization capabilities delivered a push-button implementation that yielded 43% performance improvement over the hand optimized equivalent. In addition, the tool was used to quickly evaluate performance/area trade-offs of the algorithm, a feature especially useful for resource constrained designs.

High-Level Synthesis: Can it outperform hand-coded HDL?

SLX FPGA

Our latest white paper highlights how SLX FPGA, on a real-world case study, can both automatically insert pragmas for better performance and provide deep code insights to guide code refactoring. The final #HLS implementation optimized with SLX FPGA is 64% faster compared to the handwritten HDL implementation and is completed in a fraction of the time!

Adaptive Beamformer: An HLS Optimization Case Study with SLX FPGA

SLX FPGA

In this paper, the latency and utilization metrics of an adaptive beamforming algorithm optimized by SLX FPGA are compared to the metrics of the same algorithm hand-optimized by an HLS expert. SLX FPGA achieves a lower latency and cuts development time from weeks down to minutes, using an automated flow that eliminates the need for knowledge of the algorithm and target architecture.on embedded devices can be addressed.

Accelerating Financial Applications With SLX FPGA

SLX FPGA

In this paper, two implementations of computation intensive models for pricing options are discussed, namely the Black-Scholes and Heston pricing models. This white paper demonstrates how engineers creating FPGA-based hardware accelerators for financial market models can take advantage of SLX FPGA.

Using SLX FPGA for performance optimization of SHA-3 for HLS

SLX FPGA

Can an HLS optimization tool outperform expert-level hand-optimizations? This white paper examines how SLX FPGA is used to optimize a secure hash algorithm.

Facilitating High Level Synthesis from MATLAB generated C/C++

SLX FPGA

A use case for HLS is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler.

Optimizing Deep-Learning Inference for Embedded Devices

SLX C/C++

This white paper highlights how different challenges related to the deployment (inference) of artificial neural networks (ANNs) on embedded devices can be addressed.

SLX Multi-Objective Optimization (MOPT)

SLX C/C++

Simultaneous optimization to improve power and performance with SLX

Pushing Performance: Analysis and Optimization of Multicore Communication with SLX

SLX C/C++

How SLX can predict performances, manage communication contention and automatically map tasks to get the best out of your multicore platform.

Improving Execution Predictability on Linux with SLX

SLX C/C++

Assessing the impact of deterministic programming models on predictability of test results

Multicore Software Design for an LTE Base Station

SLX C/C++

Using SLX for Multicore Software Design of an LTE Base Station

Article - Silexica’s Hardware/Software Co-design

SLX C/C++

The Linley Group's Microprocessor Report takes an in-depth look into the features of SLX

Article - Silexica: Mastering Multicore

SLX C/C++

Paul McLellan meets our US team and takes an in-depth look at SLX where he compares manual with automated code analysis

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OUR DOCUMENTATION
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