Optimizing acceleration kernels using SLX FPGA and the bottom-up flow
In this application note, Silexica uses the Vitis quantitative finance library implementation of the Vasicek Model (v_model) as a reference design to show how designers can use SLX FPGA to optimize a kernel when using Vitis bottom-up flow.
High-Level Synthesis: Can it outperform hand-coded HDL?
Our latest white paper highlights how SLX FPGA, on a real-world case study, can both automatically insert pragmas for better performance and provide deep code insights to guide code refactoring. The final #HLS implementation optimized with SLX FPGA is 64% faster compared to the handwritten HDL implementation and is completed in a fraction of the time!
Adaptive Beamformer: An HLS Optimization Case Study with SLX FPGA
In this paper, the latency and utilization metrics of an adaptive beamforming algorithm optimized by SLX FPGA are compared to the metrics of the same algorithm hand-optimized by an HLS expert. SLX FPGA achieves a lower latency and cuts development time from weeks down to minutes, using an automated flow that eliminates the need for knowledge of the algorithm and target architecture.on embedded devices can be addressed.
In this paper, two implementations of computation intensive models for pricing options are discussed, namely the Black-Scholes and Heston pricing models. This white paper demonstrates how engineers creating FPGA-based hardware accelerators for financial market models can take advantage of SLX FPGA.