Optimizing an OpenCL AI Kernel for the data center using SLX FPGA and Vitis HLS 20.2
This application note is written for FPGA application developers using Vitis HLS 20.2 version. Read how SLX FPGA accelerates an AI-related face detection design example, leveraging the bottom-up flow of Xilinx's Vitis 2020.2 and Alveo U280 accelerator card.
Optimizing an OpenCL Kernel for the data center using SLX FPGA and Vivado HLS 20.1 or earlier
This application note is written for FPGA application developers using Vivado HLS versions 20.1 and earlier. Read how SLX FPGA accelerates a Fintech design example, leveraging Xilinx's Vitis Platform's bottom-up flow, Alveo U200 accelerator card, and the Vitis quantitative finance library.
Using SLX FPGA for Performance Optimization and Design Space Exploration of a C++ Based Post-Quantum Cryptographic Algorithm
In close collaboration with NYU Tandon School of Engineering, Silexica presents a new paper to describe its use of the SLX FPGA tool to implement the signature verification portion of the Rainbow post-quantum cryptography algorithm in an FPGA. The tool's automated optimization capabilities delivered a push-button implementation that yielded 43% performance improvement over the hand optimized equivalent. In addition, the tool was used to quickly evaluate performance/area trade-offs of the algorithm, a feature especially useful for resource constrained designs.
High-Level Synthesis: Can it outperform hand-coded HDL?
Our latest white paper highlights how SLX FPGA, on a real-world case study, can both automatically insert pragmas for better performance and provide deep code insights to guide code refactoring. The final #HLS implementation optimized with SLX FPGA is 64% faster compared to the handwritten HDL implementation and is completed in a fraction of the time!
Adaptive Beamformer: An HLS Optimization Case Study with SLX FPGA
In this paper, the latency and utilization metrics of an adaptive beamforming algorithm optimized by SLX FPGA are compared to the metrics of the same algorithm hand-optimized by an HLS expert. SLX FPGA achieves a lower latency and cuts development time from weeks down to minutes, using an automated flow that eliminates the need for knowledge of the algorithm and target architecture.on embedded devices can be addressed.
In this paper, two implementations of computation intensive models for pricing options are discussed, namely the Black-Scholes and Heston pricing models. This white paper demonstrates how engineers creating FPGA-based hardware accelerators for financial market models can take advantage of SLX FPGA.