Using SLX FPGA in Financial Applications
FPGA-based accelerators are increasingly being employed in financial applications. Design, implementation and optimization of an FPGA-based accelerator is a daunting task; and often requires specialized expertise. SLX FPGA lowers the bar of the expertise required to design an FPGA-based accelerator and reduces the effort required from weeks to days. In this paper, SLX FPGA is used to accelerate optimization of FPGA implementations of two computation intensive simulations for options pricing, the Black-Scholes model and the Heston model.
Using SLX FPGA, the implementations of these models for FPGAs are optimized while using a High-Level Synthesis (HLS) based methodology. The Heston model implementation optimized with SLX outperforms the non-optimized implementation by a factor of 25x. Whereas, the Black-Scholes SLX FPGA optimized implementation achieves 29x improvement over the non-optimized version.
The following design flow steps are explored in detail in the white paper:
- Refactor non-synthesizable code for HLS – The SLX tool helps programmers with automated and guided refactoring of non-synthesizable code.
- Parallelism detection – SLX FPGA detects parallelism and guides the developer on how it can be exploited in a hardware implementation. SLX FPGA also flags roadblocks for parallelism and helps the user eliminate them to drive additional parallelism.
- HW optimization – SLX FPGA performs exploration of appropriate function pipelining and loop unrolling, providing data for the hardware through array partitioning and design space of interfaces available on the target platform.
- Pragma Insertion – Once the optimized hardware implementation is determined, SLX FPGA inserts HLS Pragmas to direct the HLS compiler on how the function should be implemented in hardware.