Using SLX FPGA for performance optimization of SHA-3 for HLS
Can an HLS optimization tool outperform expert-level hand-optimizations? A recently published white paper examines how SLX FPGA is used to optimize a secure hash algorithm; the results are compared to a competition-winning hand-optimized HLS implementation of the same algorithm. SLX provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand optimized version by 14%. Moreover, it is also more resource efficient, consuming nearly 3.6 times less look-up tables and 1.76 times less flip-flops.
The following design flow steps are explored in detail in the white paper:
- Refactor non-synthesizable code for HLS – The SLX tool helps programmers with automated and guided refactoring of non-synthesizable code.
- Parallelism detection – SLX FPGA detects parallelism and guides the developer on how it can be exploited in a hardware implementation. SLX FPGA also flags roadblocks for parallelism and helps the user eliminate them to drive additional parallelism.
- HW optimization – SLX FPGA performs exploration of appropriate function pipelining and loop unrolling, providing data for the hardware through array partitioning and design space of interfaces available on the target platform.
- Pragma Insertion – Once the optimized hardware implementation is determined, SLX FPGA inserts HLS Pragmas to direct the HLS compiler on how the function should be implemented in hardware.
Zubair Wadood is a Technical Marketing Engineer at Silexica GmbH. He completed his PhD in computer science from the University of Leuven, Belgium in 2014; his interests include embedded systems and high-performance computing. Before joining Silexica, he has worked with Mentor Graphics and u-blox.