Using High-Level Synthesis (HLS) in Radar Applications – Adaptive Beamformer Example

Posted by Jordon Inkeles
Jordon Inkeles, VP Product
| 3min to Read

As radar designs progressively move towards higher bandwidths, the latency budget for various processing components decreases. Adaptive beamforming is a critical part of modern radars. Modified Gram-Schmidt QR decomposition (MGS-QRD) and weight back substitution (WBS), are the core computational algorithms for adaptive beamforming in radars. Xilinx presents a C-based implementation of the MGS-QRD+WBS algorithm for adaptive beamforming. This implementation is manually optimized for Xilinx FPGAs using HLS pragmas and synthesized using Vivado HLS; the resulting implementation outperforms its CPU counterparts in both performance and energy efficiency by a huge margin.

Implementing the beamforming algorithm in HLS offers many benefits but the manual optimization of pragmas can take a few weeks. So, we tried using SLX FPGA to automatically generate HLS optimization pragmas for this adaptive beamforming algorithm and compare the results with the manually optimized implementation. See the SLX FPGA flow below.

SLX FPGA Flow-hls-from-matlab-generated-cc

We compare two versions of a core algorithm for adaptive beamforming. One version is manually optimized by a domain expert with considerable HLS experience. The other is automatically optimized with SLX FPGA. We estimate that an expert would require at least a week or more to analyze the application and implement optimization in the form of HLS pragmas. With SLX, this time is reduced to mere minutes. Moreover, no domain knowledge or HLS experience is required to implement these optimizations with SLX. In terms of performance, the SLX solution exceeds the speed-up obtained from manual-optimizations for a comparable cost of resources. SLX proves to be a lifesaver for developers who inherit legacy applications or new HLS users who could take months to get through the steep learning curve of HLS optimization. Experts benefit from it as well by gaining time through quick design space exploration for various optimizations and deep application analysis that helps open opportunities for further optimizations.


SLX FPGA is a powerful tool from Silexica that provides a considerable productivity boost when using high-level synthesis (HLS) to implement FPGA designs in C/C++; moreover, the performance is comparable to (often better than) hand-optimized. SLX combines static and dynamic analysis techniques to gain deep insights into the application which are then used to reason about various optimization decisions. In this beamforming example, SLX FPGA is able to achieve lower latency and cut development time from weeks down to minutes.


Interested in further details? Read and download the full white paper HERE

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Jordon Inkeles - VP Product

Jordon’s role is to drive Silexica’s product strategy including product planning and management, product marketing and corporate marketing functions. Jordon has 20+ years of experience in marketing and product management at world-leading semiconductor companies including Intel and Altera. His role at Intel PSG (Programmable Solutions Group) included leading product and corporate strategy, driving a $1 billion product line, building high-performance marketing teams and driving go-to-market strategies. Most recently, he was Director of Marketing for Intel’s Flagship Stratix Series FPGA family. For 16 years as part of Altera, before its acquisition by Intel in 2015, Jordon held senior marketing and product management positions for FPGA product families, EDA software including OpenCL, IP (Intellectual Property) and corporate marketing/communication teams.

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