The first SLX Plugin to Enhance Vitis HLS: A Successful Collaboration to Accelerate the Adoption of HLS


High-level synthesis (HLS) tools have been around for many years, but the curve of adoption is growing rapidly. The growth is coming from more mature HLS compiler tools and an increased number of SW developers looking to accelerate their application. Key benefits of the HLS tool flow include improved productivity through a higher-level of abstraction, faster verification, and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating it in RTL (register-transfer level).

However, there is still a gap existing between the software developer and the hardware implementation. Today, most C/C++ software code is inherently serial and can be performance-limited. Better performance can be achieved by moving software into hardware. Achieving significant software speed-up using hardware requires deep code insights of the algorithm and data movement to extract and exploit parallelism. HLS compilers enable users to guide the tool with pragmas or directives, but that leaves users on their own to figure out how and where to insert these pragmas. The next phase in HLS adoption will occur when HLS compilers are able to not only provide these insights but act on them based on user-provided constraints.

One step towards this vision was realized through the close collaboration between Xilinx and Silexica launching the first SLX Plugin to extend Xilinx’s Vitis HLS capabilities by enabling the addition of new pragmas and compiler optimizations when designing for FPGAs using high-level synthesis (HLS). The SLX Plugin contains the new Loop Interchange pragma, the first of many planned pragmas from Silexica that provide automatic loop transformations. In addition, the SLX Plugin contains several automatic compiler transformations that complement Vitis HLS transformations for improved performance.

Silexica’s first plugin is designed to accelerate the adoption of HLS and further expand the reach of FPGAs for software developers. When combining SLX FPGA with automatic pragma insertion and the new SLX Plugin providing new pragmas, new levels of performance and area optimization can be achieved in hardware from C/C++ code. The SLX Plugin further accelerates the path from C/C++ to FPGA.

To demonstrate the new capabilities of the SLX Plugin, Silexica is co-presenting with Xilinx at the  29th International Symposium on Field-Programmable Gate Arrays (ISFPGA) 2021, the premier conference for presentation for advances in FPGA technology. A joint presentation focusing on “Enhancing and simplifying HLS with Xilinx Vitis Open Source and Silexica tools” is part of the tutorials and workshops day and provides a deep dive into Xilinx’s open-source Clang, the Vitis HLS injection use model, and how Silexica’s SLX Plugin and SLX FPGA make use of the model to help FPGA developers achieve better results for a set of common design styles.


February, 28 2021, 8:00 AM to 10:00 AM (PST),
The event registration can be found Here

If you want to learn more about the SLX Plugin today:

Check out the evaluation written by Adam Taylor demonstrating latency reduction by more than 80% in several design examples,

MicroZed Chronicles: Vitis HLS and Silexica’s SLX Plugin


Or view Silexica’s Application Note on the SLX Plugin: Using the SLX Plugin for Vitis HLS to optimize MRI Reconstruction

The application note optimizes a Magnetic Resonance Imaging (MRI) reconstruction example by leveraging the new loop interchange pragma. The plugin guarantees a functionally correct loop interchange transformation for a pair of loops in a loop nest.

The SLX Plugin is the result of the successful collaboration between Xilinx and Silexica, showing the expertise of Silexica to tackle the challenges associated with HLS design flow. It also represents the beginning of a series of other plugins, as many more pragmas can be added to further improve the adoption of HLS.


Request a live demo today or contact us directly to learn more.

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