The AMD/Xilinx Acquisition: Software and Hardware Worlds collide again!

Posted by Maximilian Odendahl
Maximilian Odendahl, CEO and Co-Founder
| 10min to Read

Consolidation in the semiconductor industry continues with the big news last week that AMD intends to acquire Xilinx for $35B in an all-stock deal.

With FPGAs being a key ingredient to the future of both the high-performance datacenter and the intelligent edge, it is obvious why AMD is interested in this acquisition:

  • Adding Xilinx, the market-leader in customizable, adaptive hardware to their portfolio gives them access to the full computing range of CPUs, GPUs, and now FPGAs.
  • They are highly complementary companies from a product and market standpoint.
  • There is a large technology overlap in terms of packaging, integration, and foundry, with two technical leaders with common history and background at the top.

But I think there is an open big topic which hasn’t been discussed widely: expanding the addressable market of heterogeneous, adaptive hardware to software developers is a key piece that needs to be solved for both parties involved. This is especially true for next-generation datacenters (as you have C/C++ code as a starting point most of the time with pure software developer teams), where the acquisition of Xilinx makes AMD a “stronger strategic force,” according to AMD’s Lisa Su.

What’s the issue in reaching software developers today? While there are millions of developers out there, they live in a very different world with very different tools and methodologies compared to hardware designers targeting FPGAs and ASICs. The wall between those worlds will grow bigger and bigger as future hardware will become even more heterogeneous to meet performance and power requirements and more difficult to utilize, requiring very specialized programming skills and system understanding.


The industry has looked at high-level synthesis (HLS) tools like Xilinx’s Vivado/Vitis HLS or Mentor’s Catapult HLS Platform to solve the challenge when targeting FPGAs by software developers, allowing an automatic conversion from C/C++ to a hardware description language. And while there is a renewed interest recently due to the large number of newly emerging high-performance applications combined with a huge time-to-market pressure, HLS by itself is not enough to bridge the gap towards the hardware world. Software developers still need to define a custom microarchitecture with the help of so-called pragmas or compiler directives.

In order to do so, a huge amount of deep algorithmic knowledge and FPGA know-how is required. This includes a software-centric understanding of performance bottlenecks, data and control dependencies and exploitable parallelism, and a deep analysis of memory access patterns. While finding the optimal design point based on those insights is already challenging and time-consuming for hardware designers, it is completely out of reach for a software developer.

Therefore, to make customizable, heterogeneous hardware accessible to more developers and allow AMD to maximize the value of its acquisition, I believe there needs to be a much bigger investment into a software-centric ecosystem and tooling with a focus on these key areas:

  • next-generation hardware design,
  • collaborative development of joint SW/HW teams, and
  • heterogeneous system mapping.

Next-Generation Hardware Design

To make FPGAs accessible to software developers, we need the next big step in design abstraction and automation. After going from register-transfer level (in a hardware description language like VHDL or Verilog) to a higher-level abstraction in C/C++ with inline pragmas defining the microarchitecture, we now need to take the next step in design methodologies with truly automated generation of the FPGA configuration from a high-level language.

And there is great news: at Silexica, we have always had the firm belief that making FPGAs (and ASICs!) more accessible to software developers will bring a huge disruption to a variety of industries. Silexica has created a unique development platform solving this very problem. It includes next-generation hardware design with automated analysis, parallelism detection, hardware optimization, and HLS code generation, driven by a unique combination of static and dynamic code analysis as well as an incredibly fast and elaborative design space exploration, looking at billions of design points in a very smart fashion. Check out our product page here and white papers and customer success stories here.


Collaborative development of joint SW/HW teams

While software-only teams are a vision of the future we work on every day, we believe there is an important step in between in order to empower more software developers today: enabling a more productive and efficient collaboration among the algorithmic teams and the hardware designers.

Today, we are seeing those teams live in separate worlds as outlined above, with both of them having their own golden reference models and various iterations of their code, with algorithmic C/C++ code thrown over the fence and hardware designers rewriting it from scratch in a hardware description language.

Therefore, within a collaborative software development platform, algorithmic teams are able to go significantly further in the journey to customizable hardware with hardware designers acting as efficient in-house consultants, freeing them up to focus on final optimizations and overall system architecture.

This platform is truly collaborative as development happens based on the same code base as the golden reference model for all teams involved and includes full traceability over different versions, code transformations, and optimizations.

Head to my keynote from the FPGA Conference Europe 2020 to see a video outlook at the end on how we envision this collaborative future.

Heterogeneous System Mapping

Most likely you won’t use an FPGA in isolation, but it is part of a larger system, with pre- and post-processing potentially happening on other compute elements. This leads to another challenge for an optimized overall system design: system mapping (also called software distribution in some industries) and data transfer optimization. Or in much simpler terms: what part of my software should I put on either CPU, GPU, DPU, AI Accelerator, or FPGA? And how can I ensure that required data reaches those compute units fast enough?

There is no tooling out there today, but those decisions are made by system architects manually, often before any development starts based on incomplete data. And development teams are typically structured around the different compute choices, making it hard to change course if system performance is not met.

Silexica is working on tackling this issue as well, having the know-how and key technology ingredients of both software analysis and a deep understanding of heterogeneous hardware performance.


I believe combining the three items above are essential in opening up configurable hardware and heterogeneous systems to more developers, reducing the time-to-market of innovative software IP and intelligent products. They, therefore, constitute the SLX Development Platform as shown below, as we are redefining the journey from software to silicon. It is the core of our vision, “Democratizing Accelerated Computing,” and I’d love to hear your thoughts. Looking forward to discussing more!


Interested in further details about SLX FPGA?

Maximilian Odendahl-nvidia-inception-program%e3%81%a8xilinx-partner-program%e3%81%b8%e3%81%ae%e5%8f%82%e5%8a%a0%e3%81%8c%e6%b1%ba%e3%81%be%e3%82%8a%e3%81%be%e3%81%97%e3%81%9f
Maximilian Odendahl - CEO and Co-Founder

Maximilian Odendahl is on a mission to democratize accelerated computing, enabling intelligent electronic products of the future. He is the CEO and co-founder of Silexica and has built the company from its beginning in 2014 to become a global leader in software design automation for heterogeneous computing. Silexica now has a team of 60 people and has raised $28m from leading international VCs. He was selected as Germany’s Top 40 under 40 in 2019. Max received a Computer Engineering diploma from RWTH Aachen University in 2010 and was formerly the Chief Engineer of the Chair for Software for Systems on Silicon leading 15 research assistants. His work has been published in over 20 publications in international computing conferences and journals.

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