Facilitating High Level Synthesis from MATLAB® generated C/C++

A common use case for HLS is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler. This can present many challenges to the developer since there is little insight or understanding of the underlying code. SLX FPGA provides a solution to these challenges by helping the developer understand and optimize the algorithm code for HLS.

In a recently published white paper, we examine how SLX FPGA is used to take a MATLAB Embedded Coder™ generated C/C++ algorithm, in this case a Kalman filter, and optimize the C/C++ code for HLS.  In this example, SLX FPGA provides more than 62x improvement in performance after auto-insertion of HLS pragmas when compared to the solution created by the HLS compiler for the original code, which had no pragmas inserted.

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The following design flow steps are explored in detail in the white paper:

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Refactor non-synthesizable code for HLS – After generating the algorithm C/C++ code in MATLAB Embedded Coder, SLX FPGA identifies code which is non-synthesizable by HLS compilers and provides automated and guided code refactoring to transform code into HLS synthesizable code.

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Parallelism detection – SLX FPGA detects parallelism and guides the developer on how to exploit it in a hardware implementation. SLX FPGA also flags roadblocks for parallelism and helps the user eliminate them to drive additional parallelism.

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Hardware optimization – SLX FPGA performs exploration of the appropriate function pipelining and loop unrolling, providing data for the hardware through array partitioning and design space of interfaces available on the target platform.

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Pragma insertion – SLX FPGA automatically inserts HLS pragmas that guide the compiler in optimizations. HLS pragmas include various parameters that require tuning. SLX FPGA leverages static and dynamic analysis data and combines it with optimization algorithms to insert tuned and optimized pragmas based on the developer-provided constraints.

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For a detailed analysis on how to move your MATLAB Embedded coder generated algorithm to an FPGA using SLX and Vivado HLS, download our white paper, “Facilitating High Level Synthesis from MATLAB generated C/C++.” Also, please contact us if you are interested in seeing a live demo or exploring an evaluation of SLX FPGA.

Download our white paper here

Zubair Wadood-
ZUBAIR WADOOD

Zubair Wadood is a Technical Marketing Engineer at Silexica GmbH. He completed his PhD in computer science from the University of Leuven, Belgium in 2014; his interests include embedded systems and high-performance computing. Before joining Silexica, he has worked with Mentor Graphics and u-blox.

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