Exploiting Parallel Execution for Sequential Code

Adding a core can often be a quick and sometimes last-minute fix to increase computing performance. But what happens when communication between the cores actually causes more problems. Andrew Caples, VP of worldwide sales at Silexica, explains the growing trend and how early hardware exploration can offer a solution.

There are times when adding additional compute elements, processors for example, will solve a performance problem. After all, for each additional processor core added there is untapped compute capability that can be used as an offload engine for any processor already under a heavy load.

Of course there are cost, power and other implications that need to be considered. But, with so many single core SoCs available that have pin compatible dual or quad core options in the same SoC family, adding cores to meet performance requirements seems to be more commonplace.

However, a trend is appearing. It seems to be more common to see cores being added late in the design cycle and in some cases even as late as the software integration phase. Should this be a surprise?  Maybe it is feature creep? Or pushing the compute bounds too aggressively?

The software composition in complex embedded devices emanates from a variety of sources including commercial, community, silicon providers, newly developed, and legacy. This amalgamation of code transcends the software stack from device drivers, to OS, middleware, and up to the application. All of this somehow has to come together to operate flawlessly. However, what happens when performance challenges emerge? For example, experiencing system degradation due to the overhead of processing and authenticating packets (IP, CAN, whatever?), which seems like a straightforward use-case in which the packet processing tasks could be relocated to a dedicated core to resolve any performance issue. Won’t adding another core just solve the problem? Or is there a chance it can introduce other issues? For instance performance overhead associated with intra-processor communication or data access from non-local buffers for any task moved to the new core.

The fact is, there are trade-offs. For real-time systems, such as ADAS and autonomous systems, any X-Y trade-off must be considered carefully before implementation. The processing improvements gained by adding a core can easily be negated by the communication overhead between the cores. Please don’t misconstrue my point: yes, adding compute elements can improve system performance… as long as the software is designed for multicore systems.

The goal of trying exploit parallel execution for sequential code can be fraught with challenges. This wasn’t an issue in the past. Maybe because multicore systems were simulated using Virtual Prototypes or other architecture models to design and test the software in order to exploit the compute elements on the hardware before committing?  Such modeling, allowed for “what-if” software analysis. What-if there were 2 cores or 4 cores? How could the software be mapped to maximize performance and minimize overhead? Such a methodical approach most likely will yield best results. However, models can be expensive and cumbersome, and maybe even not available. If cores are being added late in the development phase, all caution is thrown to the wind, as chances are no “what-if” analysis will be possible. Multicore is a new paradigm that presents problems that cannot be solved with the same linear tools that were used in the past.

This is where Silexica comes in. Silexica introduced architecture modeling that is both scalable and configurable to be used for early hardware exploration for the next generation system, and high level to be generated quickly for the “what-if” analysis needed by the development team under the pressure of product delivery dates. Our SLX technology and engineering domain expertise can be used to help development teams exploit sequential code for parallel execution.

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ANDREW CAPLES

Andrew has over 25 years of technology sales and business development experience and drives Silexica’s growth in key vertical markets including automotive, wireless, aerospace and defense. He has presented at leading IoT and Embedded Development conferences, and published articles on diverse topics such as Security for IoT devices, and Safety for Industrial and Medical systems, and Software Optimization for Heterogeneous Multicore SoCs.

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