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Using SLX FPGA for performance optimization of SHA-3 for HLS

Posted by Zubair Wadood on Sep 26, 2019 in  Technology
In this article, it examines how SLX FPGA is used to optimize a secure hash algorithm; the result shows that SLX provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand optimized implementation by 14%.

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