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SLX FPGA

OPTIMIZED EXECUTION ON FPGAs

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Industries

Automotive

To enable advanced driver-assistance systems and autonomous driving, today's cars are becoming supercomputers on wheels. Based on high-resolution sensor data, intelligent decisions can be made in real-time. But car makers are facing the problem to implement this demanding software on low-power on-board computers. This is where SLX comes into play.
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Aerospace & Defense

To increase safety and efficiency, today’s aircrafts are becoming increasingly intelligent - whether manned or unmanned. Several data inputs from communication systems and on-board sensors are being processed in real-time. But the implementation of these navigation algorithms in a safety critical environment is still a challenge. SLX helps to meet these challenges.
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Wireless Communication

Next generation mobile networks like 5G offer radically faster connections and significantly more simultaneous users. This is enabled by mobile base stations that use hundreds of processor cores. But base station makers are facing the problem of programming these complex multicore platforms while fulfilling all timing and power requirements. This is where SLX helps.
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Robotics

Self-flying drones or autonomous robots need to understand the world around them and safely navigate in critical situations. This requires a high level of visual intelligence that is enabled by super fast image processing. But the implementation of these algorithms on a device, where every last drop of battery counts, is still a challenge. But a manageable one with SLX.
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Financial

In an ever-connected world, the speed and security of financial markets drive the global economy. In financial technology, next-generation compute acceleration is critical for improved latency, determinism, risk management, security, performance per watt, and total cost of ownership (TCO). To enable these compute requirements, financial institutions are beginning to leverage programmable hardware (FPGAs) and high-level synthesis (HLS) design methodology. With SLX, software professionals can meet these challenging system requirements with automated software optimization based on disruptive compiler technology.
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News

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The AMD/Xilinx Acquisition: Software and Hardware Worlds collide again!

Consolidation in the semiconductor industry continues with the big news that AMD intends to acquire Xilinx for $35B in an all-stock deal. Read our CEO’s thoughts.

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Silexica Extends Collaboration with Mentor for High-Level Synthesis

Silexica has announced that they will be presenting in a Virtual HLS Seminar Series organized by Mentor to show how SLX works with the Catapult™ HLS Platform.

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“SLX FPGA takes the guesswork out of high-level synthesis design. […] We were able to achieve better performance with SLX in one week compared to hand-coded RTL, which took two months.”

Philippe Manet, CEO of ECSPEC
SLX FPGA 2020.3 - Now available

SLX FPGA 2020.3 includes optimizations to the area/performance models and the optimization engine that result in 2x performance improvements for FinTech design sets compared to the previous release. These enhancements empower financial institutions and exchanges to optimize their designs and decrease time-to-market.

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The Power and Complexities of High-Level Synthesis Pragmas and Directives

Our latest blog article addresses the challenges and shows how SLX FPGA quickly guides you to the best implementation for your application!

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Recent Events

Nexstream event - Virtual
Dec 10, 2020
Nextream Solution Webinar - Virtual

On December 10th 2020, from 12:00 pm to 5:45 pm (Japanese Time – GMT+9), Silexica Japan is organizing the Nextream Solution Seminar and Silexica Technology Webinar! Connect with us and discover how SLX accelerate the journey from software to application-specific hardware systems, empowering our customers to win markets.

Register Here
DESIGN SOLUTION FORUM
Feb 12, 2021
DESIGN SOLUTION FORUM - Yokohama (Japan)

Silexica will be a sponsor at DSF Japan on February, 12th, 2021. Come to our booth to get a live demo of SLX FPGA and discover how it tackles the challenges associated with the HLS design flow including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, where to insert pragmas, and how to determine optimal SW/HW partitioning. More Information to come.

Register Here
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