Aerospace & Defense
See the SLX FPGA demos with Vitis and Vidado HLS at Xilinx Developers Forum (XDF) 2019.
This white paper examines how SLX FPGA is used to optimize a secure hash algorithm; the result shows that SLX provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand optimized implementation by 14%.
Version 2019.2 delivers 35X performance improvement with automatic HLS pragma insertion compared to no HLS pragmas. The SLX C/C++ product adds support for multi-process analysis, shared libraries, remote file systems, and improvements in graphical visualization and performance estimations.Read Story