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Silexica announces the first commercially available plugin to support Xilinx’s Vitis Unified Software Platform. The SLX Plugin is designed to expand the capabilities of the Vitis HLS tool […] when designing for FPGAs using high-level synthesis (HLS).
Read StorySilexica has announced that they will be presenting in a Virtual HLS Seminar Series organized by Mentor to show how SLX works with the Catapult™ HLS Platform.
Read Story
“SLX FPGA takes the guesswork out of high-level synthesis design. […] We were able to achieve better performance with SLX in one week compared to hand-coded RTL, which took two months.”
Silexica announces the release of SLX FPGA 2020.4 to expand the adoption of high-level synthesis (HLS) for FPGA designs. This release includes a new interactive, task-based flow that walks HLS users through the design flow from start to finish.
Read StoryOur latest blog article addresses the challenges and shows how SLX FPGA quickly guides you to the best implementation for your application!
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Recent Events
Silexica will be a sponsor at DSF Japan on February, 12th, 2021. Come to our booth to get a live demo of SLX FPGA and discover how it tackles the challenges associated with the HLS design flow including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, where to insert pragmas, and how to determine optimal SW/HW partitioning. More Information to come.
Silexica will sponsor FPGA Conference Europe 2021 organized by ELEKTRONIKPRAXIS and the Xilinx authorized training Partner PLC2. Join us on July, 6-8, 2021 and learn more about SLX FPGA. More Information to come.
